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by Aviad.H
Sun Oct 09, 2016 4:36 pm
Forum: Yocto
Topic: Parallel Camera [ANSWERED]
Replies: 3
Views: 5604

Re: Parallel Camera

Hi,
On DART-MX6 the Parallel camera interface is on IPU2_CSI1.
pinctrl_ipu1_2 section in "imxqdl-var-dart.dtsi" will be removed from .dts
as it has been mistakenly copied from "imx6qdl-var-som.dtsi"
Thanks for pointing it out.
Aviad
by Aviad.H
Wed Sep 28, 2016 11:03 am
Forum: Hardware
Topic: eth0: link is not ready
Replies: 4
Views: 8617

Re: eth0: link is not ready

Hi,
I've tested this with latest SD card image V64 and don't see any issue.
You can download the latest image from out ftp see here:
http://variwiki.com/index.php?title=VAR ... ry_V60plus
Aviad
by Aviad.H
Tue Sep 20, 2016 5:16 pm
Forum: Hardware
Topic: Can't boot from SD [SOLVED]
Replies: 2
Views: 3570

Re: Can't boot from SD

Hi, pin 57 should be left floating during boot since its part of bootstrap and in order not to interfere with internal SOM strapping. Try to remove the resistor to eliminate its value is incorrect and connect it to straight GND and test. booting from SD should read: 0x00002840 booting from NAND shou...
by Aviad.H
Mon Sep 12, 2016 1:50 pm
Forum: Hardware
Topic: JTAG debugging connections for DART-MX6
Replies: 3
Views: 4246

Re: JTAG debugging connections for DART-MX6

Hi,
That is good enough the JTAG lines are referenced to 3.3V
Aviad
by Aviad.H
Mon Sep 12, 2016 11:30 am
Forum: Hardware
Topic: JTAG debugging connections for DART-MX6
Replies: 3
Views: 4246

Re: JTAG debugging connections for DART-MX6

Hi, You can obtain VTREF and GND from VAR-DT6CustomBoard BASE_PER_3V3 and GND respectively. The are available on extension headers see page 6 of schematics: http://www.variscite.com/images/stories/DataSheets/DART-MX6/VAR-DT6CUSTOMBOARD_SCH_V1_1_Doc_V1_3.pdf For connection reference, you can also ref...
by Aviad.H
Thu Sep 08, 2016 2:44 pm
Forum: Hardware
Topic: VAR-SOM-MX6 boot / efuses
Replies: 7
Views: 7319

Re: VAR-SOM-MX6 boot / efuses

Hi,
BT_CFG2_3 is part of a resistor network and in any case this will require modification of the SOM which is not planned by us.
We currently support booting from SD2 or NAND.
Aviad
by Aviad.H
Thu Sep 08, 2016 6:28 am
Forum: Hardware
Topic: VAR-SOM-MX6 boot / efuses
Replies: 7
Views: 7319

Re: VAR-SOM-MX6 boot / efuses

Hi,
The boot mode is internal boot so EIM values override eFuses setting.
i.e. EIM is strapped via PU/PD resistors on SOM so that BT_CFG1, BT_CFG2, BT_CFG3 and BT_CFG4 have defined values as above.
if fuses were blown toggling BOOT_SEL0 would not be possible.
Aviad
by Aviad.H
Wed Sep 07, 2016 1:32 pm
Forum: Hardware
Topic: VAR-SOM-MX6 boot / efuses
Replies: 7
Views: 7319

Re: VAR-SOM-MX6 boot / efuses

Hi,
I was referring to BT_CFG1_1, BT_CFG1_2, BT_CFG1_3 which are '0'.
Full BT_CFG is:
BT_CFG1[7:0] - 11000000
BT_CFG2[7:0] - 00101000
BT_CFG3[7:0] - 00000000
BT_CFG4[7:0] - 00000000

BT_CFG2_3 is strapped logic '1' and not exposed from SOM so SD1 boot is not possible.

Aviad
by Aviad.H
Wed Sep 07, 2016 8:00 am
Forum: Hardware
Topic: VAR-SOM-MX6 boot / efuses
Replies: 7
Views: 7319

Re: VAR-SOM-MX6 boot / efuses

Hi, Default value for BOOT_CFG1, BOOT_CFG2 and BOOT_CFG3 is '0' BOOT_SEL0 is connected to BT_CFG1_7 when '0' -SD boot when '1' -NAND Boot Use command: md 0x020d8004 1 in uboot to read values of SRC_SBMR1 register (31–24 BOOT_CFG4[7:0]; 23–16 BOOT_CFG3[7:0]l;15–8 BOOT_CFG2[7:0]; 7-0 BOOT_CFG1[7:0]) b...
by Aviad.H
Thu Sep 01, 2016 6:38 am
Forum: Hardware
Topic: GPIO and UART of main processor connected to WiLink8
Replies: 5
Views: 10238

Re: GPIO and UART of main processor connected to WiLink8

Hi,
This pin is not connected so unfortunately you cannot probe it.
Aviad

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